#include #include #include #include "xperipherals_uart.h" #ifdef XPERIPHERALS_UART_1 #if XPERIPHERALS_UART_1__SUPPORT_TX //on tile[XPERIPHERALS_UART_1__TILE_NUMBER] : out port _xperipherals_uart_1__port_txd = XPERIPHERALS_UART_1__TXD_PORT; //#if $setting.handshake-mode == 1 // CTS/RTS // on tile[$resource.tile-number] : out port _xperipherals_uart_1__port_rts = $resource.rts-port; //#endif #endif #if XPERIPHERALS_UART_1__SUPPORT_RX //on tile[XPERIPHERALS_UART_1__TILE_NUMBER] : in port _xperipherals_uart_1__port_rxd = XPERIPHERALS_UART_1__RXD_PORT; //#if $setting.handshake-mode == 1 // CTS/RTS // on tile[$resource.tile-number] : out port _xperipherals_uart_1__port_cts = $resource.cts-port; //#endif #endif int _xperipherals_uart_1__period = 0; int _xperipherals_uart_1__wbusy; int _xperipherals_uart_1__rbusy; xbyte _xperipherals_uart_1__wdata; xbyte _xperipherals_uart_1__rdata; timer _xperipherals_uart_1__timer; xuint _xperipherals_uart_1__time; xuint _xperipherals_uart_1__count; #define REFERENCE_CLOCK_FREQUENCY 100000000 // Initialize internal data and state information, configure clocks and ports void xperipherals_uart_1__initialize( void ) { timer _xperipherals_uart_1__timer; #if XPERIPHERALS_UART_1__SUPPORT_TX int time; _xperipherals_uart_1__port_txd <: 1; //#if $setting.handshake-mode == 1 //_xperipherals_uart_1__port_rts <: 1; //#endif _xperipherals_uart_1__timer :> time; time += 10 * _xperipherals_uart_1__period; _xperipherals_uart_1__timer when timerafter(time) :> void; #endif #if XPERIPHERALS_UART_1__SUPPORT_RX //#if $setting.handshake-mode == 1 //_xperipherals_uart_1__port_cts <: 1; //#endif #endif _xperipherals_uart_1__wbusy = _xperipherals_uart_1__rbusy = FALSE; } // Configure clocks for a new MCLK frequency or sample rate void xperipherals_uart_1__configure( xuint baud_rate, xuint timeout_usec ) { //_xperipherals_uart_1__bit_period_1 = (1 * REFERENCE_CLOCK_FREQUENCY) / (2 * baud_rate); _xperipherals_uart_1__period = (2 * REFERENCE_CLOCK_FREQUENCY) / (2 * baud_rate); } #if XPERIPHERALS_UART_1__SUPPORT_TX void xperipherals_uart_1__write_byte( xbyte data ) { // Serial: START ................ 1 Byte of Data ............... STOP // Output: LLLLL 11111 22222 33333 44444 55555 66666 77777 88888 HHHHH // Timing: A B C D E F G H I J timer _xperipherals_uart_1__timer; int time; _xperipherals_uart_1__timer :> time; _xperipherals_uart_1__port_txd <: 0; time += _xperipherals_uart_1__period; _xperipherals_uart_1__timer when timerafter(time) :> void; // A #pragma loop unroll for( int i = 0; i < 8; ++i ) // B,C,D,E,F,G,H,I { _xperipherals_uart_1__port_txd <: ((unsigned int)data & 1); data >>= 1; time += _xperipherals_uart_1__period; _xperipherals_uart_1__timer when timerafter(time) :> void; } _xperipherals_uart_1__port_txd <: 1; time += _xperipherals_uart_1__period; _xperipherals_uart_1__timer when timerafter(time) :> void; // J } void xperipherals_uart_1__begin_write( xbyte data ) { _xperipherals_uart_1__wdata = data; _xperipherals_uart_1__count = 0; _xperipherals_uart_1__timer :> _xperipherals_uart_1__time; _xperipherals_uart_1__port_txd <: 0; _xperipherals_uart_1__time += _xperipherals_uart_1__period; _xperipherals_uart_1__wbusy = TRUE; } select xperipherals_uart_1__continue_wr( int& done ) { case _xperipherals_uart_1__wbusy => _xperipherals_uart_1__timer when timerafter(_xperipherals_uart_1__time) :> void: if( _xperipherals_uart_1__count == 0 ) { _xperipherals_uart_1__port_txd <: ((unsigned int)_xperipherals_uart_1__wdata & 1); _xperipherals_uart_1__wdata >>= 1; _xperipherals_uart_1__time += _xperipherals_uart_1__period; ++_xperipherals_uart_1__count; done = FALSE; } else if( _xperipherals_uart_1__count <= 8 ) { _xperipherals_uart_1__port_txd <: ((unsigned int)_xperipherals_uart_1__wdata & 1); _xperipherals_uart_1__wdata >>= 1; _xperipherals_uart_1__time += _xperipherals_uart_1__period; ++_xperipherals_uart_1__count; done = FALSE; } else if( _xperipherals_uart_1__count <= 20 ) { _xperipherals_uart_1__port_txd <: 1; _xperipherals_uart_1__time += _xperipherals_uart_1__period; ++_xperipherals_uart_1__count; done = _xperipherals_uart_1__count == 20; _xperipherals_uart_1__wbusy = !done; } break; } #endif #if XPERIPHERALS_UART_1__SUPPORT_RX void xperipherals_uart_1__read_byte( xbyte& data ) { timer _xperipherals_uart_1__timer; xbyte bit; int time; // Wait for START bit (Step A) _xperipherals_uart_1__port_rxd when pinseq(0) :> void; _xperipherals_uart_1__timer :> time; time += _xperipherals_uart_1__period / 2; // Sample 8 bits (Steps B,C,D,E,F,G,H,I) #pragma loop unroll for( int i = 0; i < 8; ++i ) { time += _xperipherals_uart_1__period; _xperipherals_uart_1__timer when timerafter(time) :> void; _xperipherals_uart_1__port_rxd :> bit; data = (data>>1) + (bit<<7); } // Wait for STOP bit to pass ... time += _xperipherals_uart_1__period; _xperipherals_uart_1__timer when timerafter(time) :> void; } void xperipherals_uart_1__begin_read( void ) { _xperipherals_uart_1__count = 0; _xperipherals_uart_1__timer :> _xperipherals_uart_1__time; _xperipherals_uart_1__time += _xperipherals_uart_1__period; _xperipherals_uart_1__rbusy = TRUE; } select xperipherals_uart_1__continue_rd( int& done, unsigned char& data ) { case _xperipherals_uart_1__rbusy => _xperipherals_uart_1__timer when timerafter(_xperipherals_uart_1__time) :> void: if( _xperipherals_uart_1__count == 0 ) { _xperipherals_uart_1__time += _xperipherals_uart_1__period; ++_xperipherals_uart_1__count; done = FALSE; } else if( _xperipherals_uart_1__count <= 8 ) { _xperipherals_uart_1__time += _xperipherals_uart_1__period; ++_xperipherals_uart_1__count; done = FALSE; } else if( _xperipherals_uart_1__count <= 20 ) { _xperipherals_uart_1__time += _xperipherals_uart_1__period; ++_xperipherals_uart_1__count; done = _xperipherals_uart_1__count == 20; _xperipherals_uart_1__rbusy = FALSE; } break; } #endif #endif